1. Field of the Invention
This invention relates to integrated circuit fabrication, and more particularly, to a semiconductor device having self-aligned low-resistance source, drain and gate structures and to a method for producing this device.
2. Description of the Relevant Art
Advances in computer technology, among other factors, result in a continual demand for faster integrated circuits. Integrated circuit speed may be limited by various factors, such as circuit architecture, interconnection delays, and speed limitations of individual transistors. Such transistor speed limitations may often be described in terms of RC time constants, where R and C are resistance and capacitance, respectively, associated with the transistor structure. RC time constants characterize the time needed for a transistor to turn on or off, so that transistor speed may be increased by making RC time constants as low as possible. One type of resistance associated with a transistor structure is series resistance, or resistance encountered by carriers traveling within a given portion of the transistor, such as the source of a MOSFET. Contact resistance, the resistance associated with a contact to a transistor region, is another type.
Both series and contact resistance are associated with source, drain, and gate regions of MOS transistors. Series resistance is related to the resistivity of the doped silicon typically used for source, drain and gate regions, while contact resistance is related to the resistance of the junction formed between such a silicon source, drain or gate region and an interconnect, which is typically formed from metal. A partial cross-sectional view of a conventional MOSFET structure is shown in FIG. 1. Gate dielectric 12 and polysilicon gate conductor 14 are formed upon silicon substrate 10 by deposition and patterning of dielectric and polysilicon layers. Source and drain regions 16 are of opposite carrier type than substrate 10. No patterning step is needed for introduction of source and drain 16, since these impurity distributions are typically introduced after formation of gate conductor 14. Gate conductor 14 serves as a mask to exclude the dopants forming source and drain 16 from the transistor channel underlying gate dielectric 12. Because photolithography and the associated alignment process is not used in forming source and drain 16, the source and drain are said to be "self-aligned" to the gate. The transistor and the fabrication method used to form it are also often described as self-aligned.
Self-aligned source/drain regions such as regions 16 in FIG. 1 exhibit minimal overlap with the transistor gate, minimizing the parasitic capacitances that can increase RC time constants and limit high-frequency transistor performance. In addition, the self-alignment process allows smaller feature sizes to be used, because the size tolerances which must be left to allow for lithographic alignment error are not needed. The use of conventional self-aligned processes does impose limitations upon transistor fabrication, however. For example, the use of impurity regions in the semiconductor substrate to form the source and drain necessitates high-temperature (greater than about 900.degree. C.) processing to activate impurities and anneal substrate damage, if the source and drain impurities are introduced by ion implantation (as is generally the case). Alternative impurity introduction methods such as diffusion also involve high-temperature processes. The choice of gate materials is therefore limited, because the gate must be able to withstand the high-temperature source/drain processing. In part for this reason, the current material of choice for gate conductors in MOSFET fabrication is polycrystalline silicon, or polysilicon. The resistivity of a polysilicon gate conductor is typically lowered by doping, which is often performed by ion implantation, using the same implants which dope the self-aligned source and drain.
Problems can arise with this doping, however, in part because of the different rates of dopant diffusion in polysilicon as opposed to single-crystal silicon. Although typical gate conductor thicknesses are greater than the depths of the shallow junctions required for source and drain regions in high-performance devices, diffusion rates along the grain boundaries of polycrystalline films can be on the order of one hundred times as fast as in single-crystal silicon. This can allow dopants in a polysilicon gate conductor to diffuse across the thin gate dielectric and into the underlying channel region during high-temperature processes such as implant anneals. Such diffusion can leave a region of low carrier concentration in the polysilicon directly above the gate dielectric, an occurrence often called the "polysilicon depletion effect". This region of the gate conductor adjacent to the gate dielectric therefore has a higher resistivity, and the resulting device performs as if it had an increased gate dielectric thickness. Effective doping of polysilicon gate regions is further complicated in CMOS devices because of differences in diffusion behavior of boron, the typical p-channel transistor dopant, and arsenic, the typical n-channel transistor dopant. Boron diffuses more rapidly in polysilicon than arsenic, which tends to segregate at grain boundaries. Adequate activation of arsenic impurities throughout the gate conductor of an n-channel device without causing excessive boron diffusion and polysilicon depletion effects in a p-channel device presents significant challenges.
A gate conductor made from a low-resistance metal would alleviate many of the problems with polysilicon gate conductors discussed above. Unfortunately, low-resistance metals such as aluminum are not able to withstand the high-temperature processing needed, for example, to anneal the as-implanted source and drain regions employed within a standard self-aligned process. It would therefore be desirable to develop a method of forming self-aligned gates using low-resistance metals or metal alloys. The desired method should further provide low-resistance source and drain regions, and low-resistance contacts to source, drain and gate regions so that series and contact resistances associated with the resulting transistor are reduced.